Integrated circuits are produced as a plurality of dies on a semiconductor wafer. The semiconductor wafer is subjected to various processing steps, including: forming active areas within the semiconductor material by use of doping and ion implantation; deposition and patterning of insulator layers; and forming conductor layers such as metallic layers. The insulator layers are formed over the semiconductor substrate, and are also formed between and surrounding conductor layers and over the entire structure to provide electrical insulation between layers of conductors. The conductor layers include materials such as doped polysilicon, aluminum, and copper conductor layers. Another insulator layer is formed over the entire device and is referred to as the “passivation layer” or sometimes referred to as a “protective overcoat” or “PO” layer. The passivation layer provides electrical insulation as well as protection from moisture and other impurities that can corrode or adversely affect the conductors and the semiconductor substrate. The insulator layers are thin, brittle layers of materials that can be sometimes be considered ceramic materials, such as silicon dioxide, silicon nitride, silicon oxynitride, silicon carbide, and polyimide.
After the integrated circuits are completely manufactured but while the integrated circuits still reside on a single semiconductor wafer, the devices are separated one from another. This operation is referred to as “singulation” or “dicing” of the semiconductor wafer. Singulation of integrated circuit devices from a semiconductor wafer includes physically separating the devices by a sawing or scribing operation. Mechanical sawing or laser sawing is used to saw through the semiconductor wafer in kerf lanes or scribe street areas that are defined between the integrated circuit dies. Sometimes the separation is performed by laser scribing followed by a mechanical breaking operation along a scribed area.
Because the scribe street areas are portions of the semiconductor wafer that are subjected to the same processing steps and conditions as the integrated circuit dies, and which can contain conductors and insulators as well as active areas on the semiconductor wafer, test structures are often formed in the scribe streets. These test structures can be used to characterize the expected performance of the integrated circuit dies prior to completing the manufacturing process. If the tests on the structures in the scribe streets indicate that the expected performance of the integrated circuit dies formed on the semiconductor wafer does not meet or exceed the requirements for the devices, the remaining manufacturing steps, including the use of expensive test and packaging equipment, and the use of various packaging materials, bond wires, solder balls and so forth can be saved. If the integrated circuit devices on the semiconductor wafer cannot meet the necessary performance requirements, the costs of completing these devices can be avoided. In addition, by using the test structures in the scribe streets, useful parametric information can be gathered about the devices on the semiconductor wafer without possibly damaging the bond pads in the finished integrated circuit dies. For example, parametric information on materials such as conductivity/permittivity, transistor threshold voltages, device speed and device power consumption can be obtained using test structures formed in the scribe lane areas.
Testing can be done using a wafer probe card with fine probe needles making electrical contact to bond pads or probe pads for the test structures formed in the scribe streets. Once the semiconductor wafer is diced into individual integrated circuit dies using the kerf lanes in the scribe street areas, these test structures will be destroyed.
When the semiconductor wafer is sawed, chipping of the semiconductor wafer can occur. In a mechanical dicing operation, a rotating saw blade has to cut through the insulating layers, the conductor layers, and through the semiconductor wafer. When thick metal structures are present in the saw kerf lane where the saw blade enters the semiconductor wafer, chipping problems are increased. The metal can also clog the teeth in the saw blade, causing damage to the tool and to the semiconductor wafer. The saw blade has significant vibration and heat is generated while the saw blade is rotating and cutting through these mechanically brittle layers. Use of thick metal layers to form bond or probe pads in the saw kerf lane has resulted in increased chipping and unwanted cracking in the semiconductor wafer during sawing.
Laser cutting can also be used to separate the wafer into individual integrated circuit dies. In one approach a laser is used to scribe trenches into the surface of the wafer, and the wafer is then broken mechanically along the cuts. In other approaches the laser is used to cut through the semiconductor wafer. In either of these laser dicing approaches, cracks and chipping in the semiconductor wafer can occur. These chipping and cracking problems are increased with increased metal density in the saw kerf lanes.
U.S. Pat. No. 8,309,957, filed Apr. 13, 2010, issued Nov. 13, 2012, entitled “Replacement of Scribeline Padframe with Saw-Friendly Design,” listing Chatterjee et. al. as inventors, which is co-owned with the present application and which is hereby incorporated by reference in its entirety herein, discloses reduced metal density in scribe probe pads.